View AS4C32M16MD1_9061633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AS4C32M16MD1 confidential 1 rev. 2 .0/february 2014 512m (32 m x 16 bit ) mobile ddr sdram confidential (rev . 2 . 0 , feb . /20 1 4 ) lpddr memory 512m (32m x 16bit ) mobile ddr sdram
AS4C32M16MD1 confidential 2 rev. 2 .0/february 2014 512m (32 m x 16 bit ) mobile ddr sdram confidential (rev . 2 . 0 , feb . /20 1 4 ) revision history revision no description date 1.0 initial release 2014/02/04 2.0 clock frequency to 200mhz C data rate: 400mbps C 5 n s access s p e e d option update 2014/02/17
AS4C32M16MD1 confidential 3 rev. 2 .0/february 2014 512m (32 m x 16 bit ) mobile ddr sdram confidential (rev . 2 . 0 , feb . /20 1 4 ) 1. features ? density : 512mbit ? organization - x16 bit : 8m words x 16bits x 4banks ? power supply : vdd, vddq = 1.7 to 1.95v ? speed - clock frequency : 200mhz (max.) - data rate : 400mbps (max.) ? 2kb page size - row address : a0 to a12 - column address : a0 to a9 (x16 bits) ? four internal banks for concurrent ope ration ? interface : lvcmos ? burst lengths (bl) : 2, 4, 8, 16 ? burst type (bt) - sequential : 2, 4, 8, 16 - interleave : 2, 4, 8, 16 ? cas# latency (cl) : 3 ? precharge : auto precharge option for each burst access ? driver strength : normal, 1/2, 1/4, 1/8 ? refresh : aut o - refresh, self - refresh ? refresh cycles : 8192 cycles/64ms - average refresh period : 7.8us ? operating junction temperature range - tj = - 30 to +85 ? p a c k a g e : 6 0 - b a l l f b g a ( 8 x 9 m m ) ? all parts are rohs compliant ? low power consumption ? partial array self - refresh (pasr) ? auto temperature compensated self - refresh (atcsr) by built - in temperature sensor ? deep power down mode ? burst termination by burst stop command and precharge command ? ddl is not implemented ? double - data - rate architecture : two data transfers per one clock cycle ? th e high speed data transfer is realized by the 2bits prefetch pipelined architecture ? bi - directional data strobe (dqs) is transmitted/ received with data for capturing data at the receiver ? dqs is edge - aligned with data for reads; center - aligned with data for writes ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data
AS4C32M16MD1 confidential 4 rev. 2.0/february 2014 2. general description this device is 536,870,912 bits of double data rate synchronous dram organized as 4 banks of 8,388,608 words by 16 bits. the synchronous operation with data strobe allows extremely high performance. j sc is applied to reduce leakage and refresh currents while achieving very high speed. i/o transactions are possible on both edges of the clock. the ranges of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. table 1. speed grade information speed grade C table 2 C ordering information for rohs compliant products product part no org temperature max clock (mhz) package AS4C32M16MD1 - 5 bcn 32 x 16 -30c to 85c 2 00 6 0 - ball fbga
AS4C32M16MD1 confidential 5 rev. 2 .0/february 2014 2.1 block diagram figure 2.1 block diagram
AS4C32M16MD1 confidential 6 rev. 2 .0/february 2014 2.2 package pin configurations figure 2.2 pin configurations < top view >
AS4C32M16MD1 confidential 7 rev. 2 .0/february 2014 2.4 pin description ck, ck# (input pins) the ck and the ck# are the master c lock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the ck rising edge and the ck# falling edge. when a read operation, dqss and dqs are referred to the cross point of the ck and the ck#. when a write operation, dms and dqs are referred to the cross point of the dqs and the vddq/2 level. dqss for write operation are referred to the cross point of the ck and the ck#. the other input signals are referred at ck rising edge. cs# (input pin) when cs# is low, commands and data ca n be input. when cs# is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras#, cas#, and we# (input pins) these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 to a12 (input pins) row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the ck# falling edge in a bank active command cycle. column address is l oaded at the cross point of the ck rising edge and the ck# falling edge in a read or a write command cycle (see table 2.1). this column address becomes the starting address of a burst operation. table 2.1 address pins page size organization address ( a0 to a12 ) row address column address 2kb x16 bits ax0 to ax12 ay0 to ay9 a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are pre - charged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is pre - charged. if a10 = high when read or write command, auto precharge function is enabled. ba0 and ba1 (input pins) ba0 and ba1 are b ank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see table 2.2)
AS4C32M16MD1 confidential 8 rev. 2 .0/february 2014 table 2.2 bank select signal ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h note : h = vih , l = vil cke (input pin) cke controls po wer - down mode, self - refresh function and deep power - down function with other command inputs. the cke level must be kept for 2 clocks at least, that is, if cke changes at the cross point of the ck rising edge and the ck# falling edge with proper setup time tis, by the next ck rising edge cke level must be kept with proper hold time tih. dq0 to dq15 (input/output pins) data are input to and output from these pins. udqs and ldqs (input and output pin) dqs provides the read data strobes (as output) and the write data strobes (as input). each dqs pin corresponds to eight dq pins, respectively (see table 2.3). udm and ldm (input pin) dm is the reference signals of the data input mask function. dm is sampled at the cross point of dqs and vddq/2. when dm = hig h, the data input at the same timing are masked while the internal burst counter will be counting up. each dm pin corresponds to eight dq pins, respectively (see table 2.3). table 2.3 dqs and dm correspondence organization dqs data mask dqs x16 bits ld qs ldm dq0 to dq7 udqs udm dq8 to dq15 vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers. vdd must be equal to vddq.
AS4C32M16MD1 confidential 9 rev. 2 .0/february 2014 3. command operation 3.1 simplified state diagram figure 3.1 state diagram
AS4C32M16MD1 confidential 10 rev. 2 .0/february 2014 3.2 command truth table the ddr mobile ram recognizes the following commands specified by the cs#, ras#, cas#, we# and address pins. table 3.1 command truth table command symbol cke cs# ras# cas# we# ba1 ba0 ap addr. n - 1 n ignore command desl h h h x x x x x x x no operation nop h h l h h h x x x x burst stop command bst h h l h h l x x x x column address and read command read h h l h l h v v l v read with auto precharge read a h h l h l h v v h v column address and write command writ h h l h l l v v l v write with auto precharge writa h h l h l l v v h v row address strobe and bank active act h h l l h h v v v v precharge select bank pre h h l l h l v v l x precharge all bank pall h h l l h l x x h x refresh ref h h l l l h x x x x self h l l l l h x x x x mode register set mrs h h l l l l l l l v emrs h h l l l l h l l v note : 1. h : vih , l : vil , x : don t care , v : valid address input 2. the cke level must be kept for 1 ck cycle at least. ignore command [desl] when cs# is high at the cross point of the ck rising edge and the ck# falling edge, all input signals are neglected and internal state is held. no operation [nop] as long as this command is i nput at the cross point of the ck rising edge and the ck# falling edge, address and data input are neglected and internal state is held. burst stop command [bst] this command stops a current burst operation.
AS4C32M16MD1 confidential 11 rev. 2 .0/february 2014 column address strobe and read command [read ] this command starts a read operation. the start address of the burst read is determined by the column address (see table 2.1) and the bank select address. after the completion of the read operation, all output buffers become high - z. read with auto prec harge [reada] this command starts a read operation. after completion of the read operation, precharge is automatically executed. column address strobe and write command [writ] this command starts a write operation. the start address of the burst write is determined by the column address (see table 2.1) and the bank select address. write with auto precharge [writa] this command starts a write operation. after completion of the write operation, precharge is automatically executed. row address strobe a nd bank activate [act] this command activates the bank that is selected by ba0 and ba1 (see table 2.2) and determines the row address (see table 2.1). precharge selected bank [pre] this command starts precharge operation for the bank selected by ba0 and ba1. (see table 2.2) precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts a refresh operation. there are two types of refresh operation, one is auto - refresh, and another is self - ref resh. for details, refer to the cke truth table section. mode register set/extended mode register set [mrs/emrs] the ddr mobile ram has the two mode registers, the mode register and the extended mode register, to define how it works. the both mode regis ters are set through the address pins in the mode register set cycle. for details, refer to "mode register and extended mode register set"
AS4C32M16MD1 confidential 12 rev. 2 .0/february 2014 3.3 function truth table the following tables show the operations that are performed when each command is issued in ea ch state of the ddr mobile ram. table 3.2 command truth table current state cs# ras# cas# we# address command operation pre - charging *1 h x x x x desl nop l h h h x nop nop l h h l x bst illegal *11 l h l h ba,ca,a10 read/reada ille gal *11 l h l l writ/writa illegal *11 l l h h act illegal *11 l l h l pre,pall nop l l l x x illegal idle *2 h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 read/reada illegal *11 l h l l ba,ca,a10 writ/w rita illegal *11 l l h h ba,ra act activating l l h l ba,a10 pre,pall nop l l l h x ref,self refresh / self - refresh *12 l l l l mode mrs mode register set *12 refresh (auto refresh) *3 h x x x x desl nop l h h h x nop nop h h h l x bst illegal l h l x x illegal l l x x x illegal
AS4C32M16MD1 confidential 13 rev. 2 .0/february 2014 current state cs# ras# cas# we# address command operation activating *4 h x x x x desl nop l h h h x nop nop l h h l x bst illegal *11 l h l h ba,ca,a10 read/reada illegal *11 l h l l ba,ca,a10 writ/writa illegal *11 l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall illegal *11 l l l x x illegal active *5 h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 read/reada starting read operatio n l h l l ba,ca,a10 writ/writa starting read operation l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall pre - charge l l l x x illegal read *6 h x x x x desl nop l h h h x nop nop l h h l x bst burst stop l h l h ba,ca,a10 read/reada interrupting burst read operation to start new read l h l l ba,ca,a10 writ/writa illegal *13 l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall interrupting burst read operation to start pre - charge l l l x x illegal
AS4C32M16MD1 confidential 14 rev. 2 .0/february 2014 current s tate cs# ras# cas# we# address command operation read with auto pre - charge *7 h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 writ/writa illegal l l h h ba,ra act il legal *11 l l h l ba,a10 pre,pall illegal *11 l l l x x illegal write *8 h x x x x desl nop l h h h x nop nop l h h l x bst burst stop l h l h ba,ca,a10 read/reada interrupting burst write operation to start read operation l h l l ba,ca,a10 writ/writa interrupting burst write operation to start new write operation l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall interrupting write operation to start pre - charge l l l x x illegal write recove ring *9 h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l h ba,ca,a10 read/reada starting read operation l h l l ba,ca,a10 writ/writa starting new write operation l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall illegal *11 l l l x x illegal
AS4C32M16MD1 confidential 15 rev. 2 .0/february 2014 current state cs# ras# cas# we# address command operation write with auto pre - charge *10 h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 writ/wri ta illegal l l h h ba,ra act illegal *11 l l h l ba,a10 pre,pall illegal *11 l l l x x illegal note : 1. the ddr mobile ram is in "pre - charging" state for trp after precharge command is issued. 2. the ddr mobile ram reaches "idle" state trp after precharg e command is issued. 3. the ddr mobile ram is in "refresh" state for trfc after auto - refresh command is issued. 4. the ddr mobile ram is in "activating" state for trcd after act command is issued. 5. the ddr mobile ram is in "active" state after "activating" is com pleted. 6. the ddr mobile ram is in "read" state until burst data have been output and dq output circuits are turned off. 7. the ddr mobile ram is in "read with auto precharge" from reada command until burst data has been output and dq output circuits are turned off. 8. the ddr mobile ram is in "write" state from writ command to the last burst data are input. 9. the ddr mobile ram is in "write recovering" for twr after the last data are input. 10. the ddr mobile ram is in "write with auto precharge" until twr after the las t data has been input. 11. this command may be issued for other banks, depending on the state of the banks. 12. not bank - specific; requires that all banks are idle and no bursts are in progress. 13. before executing a write command to stop the preceding burst read operation, bst command must be issued. 14. h : vih , l : vil , x : don t care
AS4C32M16MD1 confidential 16 rev. 2 .0/february 2014 3.4 cke truth table table 3.3 cke truth table current state command cke cs# ras# cas# we# address note n - 1 n idle auto refresh command (ref) h h l l l h x 2 idle self refresh entry (self) h l l l l h x 2 active / idle power down entry (pden) h l l h h h x h l h x x x x idle deep power down entry (dpden) h l l h h l x 2 self refresh self refresh exit (selfx) l h l h h h x l h h x x x x power down power down exit (pdex) l h l h h h x l h h x x x x deep power down power down exit (dpdex) l h x x x x x note : 1. h : vih , l : vil , x : don t care. 2. all the banks must be in idle and no bursts in progress be fore executing this command. 3. the cke level must be kept for 1 ck cycle at least. auto - refresh command [ref] this command executes auto - refresh. the bank and the row addresses to be refreshed are internally determined by the internal refresh controller. the output buffer becomes high - z after auto - refresh start. precharge has been completed automatically after the auto - refresh. the act or mrs command can be issued trfc after the last auto - refresh command. the average refresh interval is 7.8 s. to allow for improved efficiency in scheduling, some flexibility in the absolute refresh interval is provided. a maximum of eight auto - refresh commands can be posted to the ddr mobile ram or the maximum absolute interval between any auto - refresh command and the next auto - refresh command is 8 trefi. self - refresh entry [self] this command starts self - refresh. the self - refresh operation continues as long as cke is held low. during the self - refresh operation, all row addresses are repeated refreshing by the internal r efresh controller. a self - refresh is terminated by a self - refresh exit command.
AS4C32M16MD1 confidential 17 rev. 2 .0/february 2014 power - down mode entry [pden] tpden (= 2 clocks) after the cycle when [pden] is issued, the ddr mobile ram enters into power - down mode. in power - down mode, power consumption is suppressed by deactivating the input initial circuit. power - down mode continues while cke is held low. no internal refresh operation occurs during the power - down mode. deep power - down entry [dpden] after the command execution, deep power - down mode con tinues while cke remains low. before executing deep power - down, all banks must be pre - charged or in idle state. self - refresh exit [selfx] this command is executed to exit from self - refresh mode. tsrex after [selfx], the device will be into idle state. power - down exit [pdex] the ddr mobile ram can exit from power - down mode tpdex (1 cycle min.) after the cycle when [pdex] is issued. deep power - down exit [dpdex] as cke goes high in the deep power - down mode, the ddr mobile ram exit from the deep power - do wn mode through deep power - down exiting sequence.
AS4C32M16MD1 confidential 18 rev. 2 .0/february 2014 4. device operation 4.1 initialization the ddr mobile ram is initialized in the power - on sequence according to the following. 1. provide power, the device core power (vdd) and the device i/o power (vddq) mus t be brought up simultaneously to prevent device latch - up. although not required, it is recommended that vdd and vddq are from the same power source. also assert and hold clock enable (cke) to a lv - cmos logic high level. 2. once the system has established con sistent device power and cke is driven high, it is safe to apply stable clock. 3. there must be at least 200s of valid clocks before any command may be given to the dram. during this time nop or deselect (desl) commands must be issued on the command bus. 4. iss ue a precharge all command. 5. provide nops or desl commands for at least trp time. 6. issue an auto - refresh command followed by nops or desl command for at least trfc time. issue the second auto - refresh command followed by nops or desl command for at least trfc time. note as part of the initialization sequence there must be two auto - refresh commands issued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. 7. using the mrs command, load the base mode register. set the desired operating modes. 8. provide nops or desl commands for at least tmrd time. 9. using the mrs command, program the extended mode register for the desired operating modes. 10. provide nop or desl commands for at least tmrd time. 11. the dram has been properly initi alized and is ready for any valid command. 4.2 mode register and extended mode register set there are two mode registers, the mode register and the extended mode register so as to define the operating mode. parameters are set to both through the a0 to the a 12 and ba0 and ba1 pins by the mode register set command [mrs] or the extended mode register set command [emrs]. the mode register and the extended mode register are set by inputting signal via the a0 to the a12 and ba0 and ba1 pins during mode register se t cycles. ba0 and ba1 determine which one of the mode register or the extended mode register are set. prior to a read or a write operation, the mode register must be set.
AS4C32M16MD1 confidential 19 rev. 2 .0/february 2014 4.2.1 mode register the mode register has four fields; reserved : a12 through a7 cas late ncy : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clocks have elapsed. cas# latency cas# latency must be set to 3. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high - z. the burst length is programmable as 2, 4, 8 and 16. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either sequential or interleave. burst operation shows the addressing sequence for each burst length for each wrap type. 4.2.2 extended mode register the extended mode register has three fields ; reserved : a12 through a7, a4, a3 driver strength : a6 through a5 partial array self - refresh : a2 through a0 following extended mode register programming, no command can be issued before at least 2 clocks have elapsed. driver strength by setting specif ic parameter on a6 and a5, driving capability of data output drivers is selected. auto temperature compensated self - refresh (atcsr) the ddr mobile ram automatically changes the self - refresh cycle by on die temperature sensor. no extended mode register pr ogram is required. manual tcsr (temperature compensated self - refresh) is not implemented.
AS4C32M16MD1 confidential 20 rev. 2 .0/february 2014 partial array self - refresh memory array size to be refreshed during self - refresh operation is programmable in order to reduce power. data outside the defined area will not be retained during self - refresh.
AS4C32M16MD1 confidential 21 rev. 2 .0/february 2014 4.3 power down & deep power down 4.3.1 deep power down exit sequence in order to exit from the deep power - down mode and enter into the idle mode, the following sequence is needed, which is similar to the power - on sequence . 1. a 200s or longer pause must precede any command other than ignore command (desl). 2. after the pause, all banks must be pre - charged using the precharge command (the precharge all banks command is convenient). 3. once the precharge is completed and the minimum trp is satisfied, two or more auto - refresh must be performed. 4. both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, tmrd (2 clocks minimum) pause must be satisfied. remarks: 1. the sequence of auto - refresh, mode register programming and extended mode register programming above may be transposed. 2. cke must be held high. 4.3.2 power down mode and cke control ddr mobile ram will be into power - down mode at the second ck risin g edge after cke to be low level with nop or desl command at first ck rising edge after cke signal to be low. figure 4.1 power down entry and exit
AS4C32M16MD1 confidential 22 rev. 2 .0/february 2014 notes: 1. valid*1 can be either activate command or precharge command, when valid*1 is activate command, p ower - down mode will be active power - down mode, while it will be precharge power down mode, if valid*1 will be precharge command. 2. valid*2 can be any command as long as all of specified ac parameters are satisfied. however, if the cke has one clock cycle hi gh and on clock cycle low just as below, even ddr mobile ram will not enter power - down mode, this command flow does not hurt any data and can be done. figure 4.2 cke control note: assume pre and act command is closing and activating same bank.
AS4C32M16MD1 confidential 23 rev. 2 .0/february 2014 4.4 mode r egister definition figure 4.3 mode register note: r = reserved.
AS4C32M16MD1 confidential 24 rev. 2 .0/february 2014 4.5 burst operation the burst type (bt) and the first three bits of the column address determine the order of a data out. table 4.1 burst length = 2 starting address addressing (decimal) a0 sequence interleave 0 0, 1 0, 1 1 1, 0 1, 0 table 4.2 burst length = 4 starting address addressing (decimal) a1 a0 sequence interleave 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 table 4.3 burst length = 8 starting address addressing (decimal) a2 a1 a0 sequence interleave 0 0 0 0, 1, 2, 3, 4 , 5, 6, 7 0, 1, 2, 3, 4 , 5, 6, 7 0 0 1 1, 2, 3, 4, 5 , 6, 7, 0 1, 0, 3, 2, 5 , 4, 7, 6 0 1 0 2, 3, 4, 5, 6 , 7, 0, 1 2, 3, 0, 1, 6 , 7, 4, 5 0 1 1 3, 4, 5, 6, 7 , 0, 1, 2 3, 2, 1, 0, 7 , 6, 5, 4 1 0 0 4, 5, 6, 7, 0 , 1, 2, 3 4, 5, 6, 7, 0 , 1, 2, 3 1 0 1 5, 6, 7, 0, 1 , 2, 3, 4 5, 4, 7, 6, 1 , 0, 3, 2 1 1 0 6, 7, 0, 1, 2 , 3, 4, 5 6, 7, 4, 5, 2 , 3, 0, 1 1 1 1 7, 0, 1, 2, 3 , 4, 5, 6 7, 6, 5, 4, 3 , 2 , 1, 0
AS4C32M16MD1 confidential 25 rev. 2 .0/february 2014 table 4.4 burst length = 16 starting address addressing (decimal) a3 a2 a1 a0 sequence interleave 0 0 0 0 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 0 0 0 1 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0 1,0,3,2,5,4,7 ,6,9,8,11,10,13,12,15,14 0 0 1 0 2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1 2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13 0 - 0 1 1 3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2 3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12 0 1 0 0 4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3 4,5,6,7,0,1,2 ,3,12,13,14,15,8,9,10,11 0 1 0 1 5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4 5,4,7,6,1,0,3,2,13,12,15,14,9,8,11,10 0 1 1 0 6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5 6,7,4,5,2,3,0,1,14,15,12,13,10,11,8,9 0 1 1 1 7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6 7,6,5,4,3,2,1, 0,15,14,13,12,11,10,9,8 1 0 0 0 8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7 8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7 1 0 0 1 9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8 9,8,11,10,13,12,15,14,1,0,3,2,5,4,7,6 1 0 1 0 10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9 10,11,8,9,14,15 ,12,13,2,3,0,1,6,7,4,5 1 0 1 1 11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10 11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4 1 1 0 0 12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11 12,13,14,15,8,9,10,11,4,5,6,7,0,1,2,3 1 1 0 1 13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12 13,12,15,14,9,8, 11,10,5,4,7,6,1,0,3,2 1 1 1 0 14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13 14,15,12,13,10,11,8,9,6,7,4,5,2,3,0,1 1 1 1 1 15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
AS4C32M16MD1 confidential 26 rev. 2 .0/february 2014 4.6 read / write operation bank active a read or a write operat ion begins with the bank active command [act]. the bank active command determines a bank address and a row address. for the bank and the row, a read or a write command can be issued trcd after the act is issued. read operation the burst length (bl), the cas# latency (cl) and the burst type (bt) of the mode register are referred when a read command is issued. the burst length (bl) determines the length of a sequential output data by the read command that can be set to 2, 4, 8 or 16. the starting address of the burst read is defined by the column address, the bank select address (see 2.4 pin description) in the cycle when the read command is issued. the data output timing is characterized by cl and tac. the read burst start (cl - 1) tck + tac (ns) after the clock rising edge where the read command is latched. the ddr mobile ram outputs the data strobe through dqs pins simultaneously with data. trpre prior to the first rising edge of the data strobe, the dqs pins are driven low from high - z state. this low per iod of dqs is referred as read preamble. the burst data are output coincidentally at both the rising and falling edge of the data strobe. the dq pins become high - z in the next cycle after the burst read operation completed. trpst from the last falling edge of the data strobe, the dqs pins become high - z. this low period of dqs is referred as read postamble. figure 4.4 read operation (burst length)
AS4C32M16MD1 confidential 27 rev. 2 .0/february 2014 figure 4.4 read operation (cas# length) burst stop command during burst operation the burst stop (bst) command stops the burst read and sets all output buffers to high - z. tbstz (= cl) cycles after a bst command issued, all dq and dqs pins become high - z. the bst command is also supported for the burst write operation. no data will be written in subsequent c ycles. note that bank address is not referred when this command is executed.
AS4C32M16MD1 confidential 28 rev. 2 .0/february 2014 figure 4.5 burst stop during a read operation
AS4C32M16MD1 confidential 29 rev. 2 .0/february 2014 write operation the burst length (bl) and the burst type (bt) of the mode register are referred when a write command is issued. the burst length (bl) determines the length of a sequential data input by the write command that can be set to 2, 4, 8 or 16. the latency from write command to data input is fixed to 1. the starting address of the burst write is defined by the column addr ess, the bank select address (see 2.4 pin description) in the cycle when the write command is issued. dqs should be input as the strobe for the input - data and dm as well during burst operation. twpre prior to the first rising edge of dqs, dqs must be set t o low. twpst after the last falling edge of dqs, the dqs pins can be changed to high - z. the leading low period of dqs is referred as write preamble. the last low period of dqs is referred as write post - amble. figure 4.6 write operation
AS4C32M16MD1 confidential 30 rev. 2 .0/february 2014 read with auto precharge the precharge is automatically performed after completing a read operation. the precharge starts bl/2 (= trpd) clocks after reada command input. tras lock out mechanism for reada allows a read command with auto precharge to be issued to a bank t hat has been activated (opened) but has not yet satisfied the tras (min) specification. a column command to the other active bank can be issued the next cycle after the last data output. read with auto precharge command does not limit row commands executio n for other bank.
AS4C32M16MD1 confidential 31 rev. 2 .0/february 2014 figure 4.7 read with auto precharge write with auto precharge the precharge is automatically performed after completing a burst write operation. the precharge operation is started write latency (wl) + bl/2 + twr (= twpd) clocks afte r writa command issued. a column command to the other banks can be issued the next cycle after the internal precharge command issued. write with auto precharge command does not limit row commands execution for other bank. figure 4.8 burst write (bl = 4)
AS4C32M16MD1 confidential 3 2 rev. 2 .0/february 2014 the concurrent auto precharge the ddr mobile ram supports the concurrent auto precharge feature, a read with auto precharge or a write with auto precharge, can be followed by any command to the other banks, as long as that command does not interrupt th e read or write data transfer, and all other related limitations apply (e.g. contention between read data and write data must be avoided.) the minimum delay from a read or write command with auto precharge, to a command to a different bank, is summarized b elow. table 4.5 the minimum delay from a read or write command with auto precharge from command to command (different bank, non - interrupting command) minimum delay (concurrent ap supported) unit read with auto precharge read or read w/ap bl / 2 tck write or write w/ap cl (rounded up) + (bl/2) precharge or activate 1 write with auto precharge read or read w/ap 1 + (bl/2) + twtr write or write w/ap bl / 2 precharge or activate 1
AS4C32M16MD1 confidential 33 rev. 2 .0/february 2014 4.7 command intervals 4.7.1 read command to the consecutiv e read command interval table 4.6 a read command to the consecutive read command interval destination row of the consecutive read command operation bank address row address state 1 same same active the consecutive read can be performed after a n interval of no less than 1 cycle to interrupt the preceding read operation. 2 same different - precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. see a interval 3 different any active the consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. idle precharge the bank without interrupting the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. figure 4.9 read to read command interval (same row address in the same bank)
AS4C32M16MD1 confidential 34 rev. 2 .0/february 2014 figure 4.10 read to read command interval (different bank)
AS4C32M16MD1 confidential 35 rev. 2 .0/february 2014 4.7.2 a write command to the consecutive write command interval table 4.7 a write command to the consecutive write command interval destination row of the consecutive write command operation bank address row address state 1 same same active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. 2 same differ ent - precharge the bank to interrupt the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. see a val 3 different any active the consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. idle precharge the bank without interrupting the preceding write oper ation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued.
AS4C32M16MD1 confidential 36 rev. 2 .0/february 2014 figure 4.11 write to write command interval (same row address in the same bank) figure 4.12 write to write comma nd interval (different bank)
AS4C32M16MD1 confidential 37 rev. 2 .0/february 2014 destination row of the consecutive write command operation bank address row address state 1 same same active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive wri te command can be issued. 2 same different - precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. see a read command to the consecutive precharge interval section. 3 different any active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. idle precharge the bank independently of the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. 4.7.3 a read command to the consecutive write command interval with bst command table 4.8 a read command to the consecutive write command interval with bst command
AS4C32M16MD1 confidential 38 rev. 2 .0/february 2014 figure 4.13 read to write command in terval
AS4C32M16MD1 confidential 39 rev. 2 .0/february 2014 4.7.4 a write command to the consecutive read command interval : to complete the burst operation table 4.9 a write command to the consecutive read command interval : to complete the burst operation destination row of the consecutive read command o peration bank address row address state 1 same same active to complete the burst operation, the consecutive read command should be performed twrd after the write command. 2 same different - precharge the bank twpd after the preceding wri te command. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. see a interval 3 different any active to complete a burst operation, the consecutive read command should be performed twrd after the write command. idle precharge the bank independently of the preceding write operation. trp after the precharge command, issue the act command. trcd after the act comm and, the consecutive read command can be issued.
AS4C32M16MD1 confidential 40 rev. 2 .0/february 2014 figure 4.14 write to read command interval
AS4C32M16MD1 confidential 41 rev. 2 .0/february 2014 4.7.5 a write command to the consecutive read command interval : to interrupt the write operation table 4.10 a write command to the consecutive read command interv al : to interrupt the write operation destination row of the consecutive read command operation bank address row address state 1 same same active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. 2 same different - note 1 3 different any active dm must be input 1 cycle prior to the read command input to prevent from being written in valid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. idle note 1 note : 1. precharge must be preceded to read command. therefore read command can n ot interrupt the write operation in this case. figure 4.15 write to read command interval (same bank, same row address) [write to read delay = 1 clock cycle]
AS4C32M16MD1 confidential 42 rev. 2 .0/february 2014 figure 4.16 write to read command interval (same bank, same row address) [write to read delay = 2 clock cycle] figure 4.17 write to read command interval (same bank, same row address) [write to read delay = 4 clock cycle] note : twtr is referenced from the first positive ck edge after the last desired data in pair twtr.
AS4C32M16MD1 confidential 43 rev. 2 .0/february 2014 4.7.6 a write command to the burst stop command interval : to interrupt the write operation figure 4.18 write to bst command interval (same bank, same row address) [write to bst delay = 1 clock cycle] figure 4.19 write to bst command interval (same bank, same row address) [write to bst delay = 2 clock cycle]
AS4C32M16MD1 confidential 44 rev. 2 .0/february 2014 figure 4.20 write to bst command interval (same bank, same row address) [write to bst delay = 3 clock cycle] 4.7.7 a read command to the consecutive precharge command i nterval operation by each case of destination bank of the consecutive precharge command. table 4.11 a read command to the consecutive precharge command interval bank address operation 1 same the pre and pall command can interrupt a read operation . to complete a burst read operation, trpd is required between the read and the precharge command. please refer to the following timing chart. 2 different the pre command does not interrupt a read command. no interval timing is required between the read and the precharge command.
AS4C32M16MD1 confidential 45 rev. 2 .0/february 2014 read to precharge command interval (same bank) : to output all data to complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued trpd (= bl/ 2 cycles) after t he read command is issued. figure 4.21 read to precharge command interval (same bank) : [to output all data (cl=3, bl=4)] read to precharge command interval (same bank): to stop output data a burst data output can be interrupted with a precharge command. all dq pins and dqs pins become high - z thzp (= cl) after the precharge command. figure 4.22 read to precharge command interval (same bank) : [to stop output data (cl=3, bl=4, 8)]
AS4C32M16MD1 confidential 46 rev. 2 .0/february 2014 4.7.8 a write command to the consecutive precharge comma nd interval (same bank) operation by each case of destination bank of the consecutive precharge command. table 4.12 a write command to the consecutive precharge command interval (same bank) bank address operation 1 same the pre and pall command c an interrupt a write operation. to complete a burst write operation, twpd is required between the write and the precharge command. please refer to the following timing chart. 2 different the pre command does not interrupt a write command. no interval timing is required between the write and the precharge command. write to precharge command interval (same bank) the minimum interval twpd is necessary between the write command and the precharge command. figure 4.23 write to precharge comma nd interval (same bank) : bl=4
AS4C32M16MD1 confidential 47 rev. 2 .0/february 2014 figure 4.24 write to precharge command interval(same bank):bl=4, dm to mask data 4.7.9 bank active command interval table 4.13 bank active command interval destination row of the consecutive act command operation ba nk address row address state 1 same any active two successive act commands can be issued at trc interval. in between two successive act operations, precharge command should be executed. 2 different any active precharge the bank. trp af ter the precharge command, the consecutive act command can be issued. idle trrd after an act command, the next act command can be issued.
AS4C32M16MD1 confidential 48 rev. 2 .0/february 2014 figure 4.25 bank active mode register set to bank - active command interval the interval between setting the mode register and executing a bank - active command must be no less than tmrd. figure 4.26 mode register set to bank active
AS4C32M16MD1 confidential 49 rev. 2 .0/february 2014 4.7.10 dm control dm can mask input data. by setting dm to low, data can be written. udm and ldm can mask the upper and lower byte of input data, respectively. when dm is set to high, the corresponding data is not written, and the previous data is held. the latency between dm input and enabling/disabling mask function is 0. figure 4.27 dm control
AS4C32M16MD1 confidential 50 rev. 2 .0/february 2014 5. timing waveforms figure 5.1 com mand and address input timing definition
AS4C32M16MD1 confidential 51 rev. 2 .0/february 2014 figure 5.2 read timing definition - 1
AS4C32M16MD1 confidential 52 rev. 2 .0/february 2014 figure 5.2 read timing definition C 2
AS4C32M16MD1 confidential 53 rev. 2 .0/february 2014 figure 5.3 write timing definition
AS4C32M16MD1 confidential 54 rev. 2 .0/february 2014 figure 5.4 initialize sequence
AS4C32M16MD1 confidential 55 rev. 2 .0/february 2014 figure 5.5 read cycle
AS4C32M16MD1 confidential 56 rev. 2 .0/february 2014 figure 5.6 write cycl e
AS4C32M16MD1 confidential 57 rev. 2 .0/february 2014 figure 5.7 mode register set cycle
AS4C32M16MD1 confidential 58 rev. 2 .0/february 2014 figure 5.8 read / write cycle
AS4C32M16MD1 confidential 59 rev. 2 .0/february 2014 figure 5.9 auto refresh cycle
AS4C32M16MD1 confidential 60 rev. 2 .0/february 2014 figure 5.10 self refresh cycle
AS4C32M16MD1 confidential 61 rev. 2 .0/february 2014 figure 5.11 power down entry and exit
AS4C32M16MD1 confidential 62 rev. 2 .0/february 2014 figure 5.12 deep power down entry
AS4C32M16MD1 confidential 63 rev. 2 .0/february 2014 figure 5.13 de ep power down exit note: the sequence of auto - refresh, mode register programming and extended mode register programming above may be transposed.
AS4C32M16MD1 confidential 64 rev. 2 .0/february 2014 6. electrical specifications ? all voltages are referenced to vss (gnd). ? after power - up, wait more than 200s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. 6.1 absolute maximum ratings table 6.1 absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt - 0.5 to +2.3 v supply voltage relative to vss vdd - 0.5 to +2.3 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating junction temperature tj - 30 to +85 storage temperature tstg - 55 to +125 caution : exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum ratin g conditions for extended periods may affect device reliability.
AS4C32M16MD1 confidential 65 rev. 2 .0/february 2014 6.2 dc characteristics table 6.2 recommended dc operating conditions (tj= - 30 to +85 ) parameter pins symbol min. typ. max. unit note supply voltage vdd, vddq 1.7 1.8 1.95 v 1 vss, vssq 0 0 0 input high voltage all other input pins vih 0.8 x vddq - vddq + 0.3 v input low voltage vil - 0.3 - 0.2 x vddq v dc i nput voltage level ck, ck# vin(dc) - 0.3 - vddq + 0.3 v ac input differential cross point voltage vix 0.4 x vddq 0.5 x vddq 0.6 x vddq 6 dc input differential voltage vid(dc) 0.4 x vddq - vddq + 0.6 5 ac input differentia l voltage vid(ac) 0.6 x vddq - vddq + 0.6 5 dc input high voltage dq, dm, dqs vihd(dc) 0.7 x vddq - vddq + 0.3 v dc input low voltage vild(dc) - 0.3 - 0.3 x vddq ac input high voltage vihd(ac) 0.8 x vddq - vddq + 0.3 ac input low voltage vild(ac) - 0.3 - 0.2 x vddq notes: 1. vddq must be equal to vdd. 2. vih (max.) = 2.3v (pulse width 5ns). 3. vil (min.) = C 0.5v (pulse width 5ns). 4. all voltage referred to vss and vssq must be same potential. 5. vid (dc) and vid (ac) a re the magnitude of the difference between the input level on ck and the input level on ck#. 6. the value of vix is expected to be 0.5 vddq and must track variations in the dc level of the same.
AS4C32M16MD1 confidential 66 rev. 2 .0/february 2014 table 6.3 dc characteristics - i ( tj = - 30 to +85 , vdd and v ddq = 1.7v to 1.95v, vss and vssq = 0v) parameter symbol max. unit test condition operating current (act - pre) idd0 85 ma one bank active - precharge, cke = h, cs# = h between valid commands, tck = tck (min.), trc = trc (min.), address bus inpu ts are switching; data bus inputs are stable standby current in power down idd2p 0.8 ma all banks idle, cke=l, cs#=h, tck=tck (min.), address and control inputs are switching; data bus inputs are stable standby current in power down with clock stop i dd2ps 0.6 ma all banks idle, cke=l, cs#=h, ck=l, ck#=h, address and control inputs are switching; data bus inputs are stable standby current in non - power down idd2n 7.0 ma all banks idle, cke=h, cs#=h, tck=tck (min.), address and control inputs are s witching; data bus inputs are stable standby current in non - power down with clock stop idd2ns 2.0 ma all banks idle, cke=h, cs#=h, ck=l, ck#=h, address and control inputs are switching; data bus inputs are stable active standby current in power down idd3p 3.0 ma one bank active, cke=l, cs#=h, tck=tck (min.), address and control inputs are switching; data bus inputs are stable active standby current in power down with clock stop idd3ps 2.0 ma one bank active, cke=l, cs#=h, ck=l, ck#=h; address a nd control inputs are switching; data bus inputs are stable active standby current in non - power down idd3n 10 ma one bank active, cke=h, cs#=h, tck=tck (min.), address and control inputs are switching; data bus inputs are stable active standby curren t in non - power down with clock stop idd3ns 7.0 ma one bank active, cke=h, cs#=h, ck=l, ck#=h, address and control inputs are switching; data bus inputs are stable burst operating current idd4 135 ma one bank active, continuous burst reads or wr ites; tck=tck (min.), cl=3, bl=4, iout = 0ma, address inputs are switching, 50% data change each burst transfer auto - refresh current idd5 90 ma cke=h, tck=tck (min.), trfc=trfc (min.), address and control inputs are switching; data bus inputs are st able deep power down current idd8 10 ua address and control inputs are stable; data bus inputs are stable
AS4C32M16MD1 confidential 67 rev. 2 .0/february 2014 table 6.4 advanced data retention current (tj = ? 30 c to +85 c, vdd and vddq = 1.7v to 1.95v, vss and vssq = 0v) parameter symbol typ. max. unit condition advanced data retention current (self refresh current) pasr="000" (full) idd6 - 400 ua - 30c tj +40c cke = l pasr="001" (2bk) - 350 pasr="010" (1bk) - 330 pasr="000" (full) idd6 - 600 +40c < tj +70 c cke = l pasr="001" (2bk) - 450 pasr="010" (1bk) - 380 pasr="000" (full) idd6 - 700 +70c < tj +85c cke = l pasr="001" (2bk) - 500 pasr="010" (1bk) - 400 notes: 1. idd specifications are tested after the device is properly initializ ed. 2. input slew rate is specified by test conditions. 3. definitions for idd: l is defined as vin 0.1 vddq; h is defined as vin 0.9 vddq; stable is defined as inputs stable at an h or l level; switching is defined as: address and command: inputs changi ng between h and l once per two clock cycles; data bus inputs: dq changing between h and l once per clock cycle; dm and dqs are stable. table 6.5 dc characteristics - ii (tj= - 30 to +85 , vdd and vddq = 1.7v to 1.95v, vss and vssq = 0v) parameter symbol min. max. unit test condition input leakage current ili - 2.0 2.0 ua 0 vin vddq output leakage current ilo - 1.5 1.5 ua 0 vout vddq, dq = disable output high voltage voh 0.9 x vddq - v ioh = - 0.1ma output low voltage vol - 0.1 x vddq v iol = 0.1 ma
AS4C32M16MD1 confidential 68 rev. 2 .0/february 2014 table 6.6 pin capacitance (ta = +25c, vdd and vddq = 1.7v to 1.95v) parameter symbol pins min. typ. max. unit note input capacitance cl1 cl2 cdi1 ck, ck# all other i ck, ck# nput only pins 1.5 1.5 - - - - 3.5 3.0 0.25 1 1 1 delta input capacitance cdi2 all other input only pins - - 0.5 pf 1 data input/output capacitance ci/o dq, dm, dqs 2.0 - 4.5 1,2 delta input/output capacitance cdio dq, dm, dqs - - 0.5 1 notes: 1. these parameters are me asured on conditions: f = 100mhz, vout = vddq/2, vout = 0.2v, ta = +25c. 2. dout circuits are disabled.
AS4C32M16MD1 confidential 69 rev. 2 .0/february 2014 6.3 ac characteristics table 6.7 ac characteristics (reference) (tj= - 30 to +85 , vdd and vddq = 1.7v to 1.95v, vss and vssq = 0v) parameter symbol m in. max. unit note clock cycle time tck 5.0 - ns ck high - level width tch 0.45 0.55 tck ck low - level width tcl 0.45 0.55 tck ck half period thp min. (tch,tcl) - tck dq output access time from ck, ck# tac 2.0 5.0 ns 2, 8 dqs - in cycle time td sc 0.9 1.1 tck dqs output access time from ck, ck# tdqsck 2.0 5.0 ns 2, 8 dq - out high - impedance time from ck, ck# thz - 5.0 ns 5, 8 dq - out low - impedance time from ck, ck# tlz 1.0 - ns 6, 8 dqs to dq skew tdqsq - 0.4 ns 3 dq/dqs output hold time from dqs tqh thp - tqhs - ns 4 data hold skew factor tqhs - 0.5 ns dq and dm input setup time tds 0.5 - ns 3 dq and dm input hold time tdh 0.5 - ns 3 dq and dm input pulse width tdipw 1.6 - ns read preamble trpre 0.9 1.1 tck read post - amble trpst 0.4 0.6 tck write preamble setup time twpres 0 - ns write preamble twpre 0.25 - tck write post - amble twpst 0.4 0.6 tck 7 write command to first dqs latching transition tdqss 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 - tck
AS4C32M16MD1 confidential 70 rev. 2 .0/february 2014 dqs fa lling edge hold time from ck tdsh 0.2 - tck dqs input high pulse width tdsh 0.4 - tck dqs input low pulse width tdqsl 0.4 - tck address and control input setup time tis 0.9 - ns 3 address and control input hold time tih 0.9 - ns 3 address and contr ol input pulse width tipw 2.3 - ns 3 mode register set command cycle time tmrd 2 - tck active to precharge command period tras 40 120000 ns active to active/auto - refresh command period trc 55 - ns auto - refresh to active/auto - refresh command period t rfc 96 - ns active to read/write delay trcd 15 - ns precharge to active command period trp 15 - ns column address to column address delay tccd 1 - tck active to active command period trrd 10 - ns write recovery time twr 15 - ns auto pre - charge write recovery and pre - charge time tdal - - - 9 self - refresh exit period tsrex 120 - ns power - down entry tpden 2 - tck power - down exit to command input tpdex 1 - tck internal write to read command delay twtr 2 - tck refresh period tref - 64 ms a verage periodic refresh interval trefi - 7.8 us cke minimum pulse width tcke 2 - tck write to pre - charge command delay (same bank) twpd 4+bl/2 - tck read to pre - charge command delay (same bank) trpd bl/2 - tck write to read command delay (to input all data) twrd 3+bl/2 - tck
AS4C32M16MD1 confidential 71 rev. 2 .0/february 2014 burst stop command to write command delay (cl = 3) tbstw 3 - tck
AS4C32M16MD1 confidential 72 rev. 2 .0/february 2014 burst stop command to dq high - z (cl = 3) tbstz 3 - tck read command to write command delay (to output all data) (cl = 3) trwd 3+bl/2 - tck pre - charge command to high - z (cl = 3) thzp 3 - tck mode register set command cycle time tmrd 2 - tck notes: 1. o n all ac measurements, we assume the test conditions shown in test conditions and full driver strength is assumed for the output load, that is both a6 and a5 of emrs is set to be l. 2. this parameter defines the signal transition delay from the cross point of ck and ck#. the signal transition is defined to occur when the signal level crossing vddq/2. 3. the timing reference level is vddq/2. 4. output valid wind ow is defined to be the period between two successive transitions of data out signals. the signal transition is defined to occur when the signal level crossing vddq/2. 5. thz is defined as dout transition delay from low - z to high - z at the end of read burst ope ration. the timing reference is cross point of ck and ck#. this parameter is not referred to a specific dout voltage level, but specify when the device output stops driving. 6. tlz is defined as dout transition delay from high - z to low - z at the beginning of r ead operation. this parameter is not referred to a specific dout voltage level, but specify when the device output begins driving. 7. the transition from low - z to high - z is defined to occur when the device output stops driving. a specific reference voltage to judge this transition is not given. 8. tac, tdqsck, thz and tlz are specified with 15pf bus loading condition. 9. minimum 3 clocks of tdal (= twr + trp) is required because it need minimum 2 clocks for twr and minimum 1 clock for trp. tdal = (twr/tck) + (trp/tc k): for each of the terms above, if not already an integer, round to the next higher integer.
AS4C32M16MD1 confidential 73 rev. 2 .0/february 2014 6.4 test conditions table 6.8 test conditions parameter symbol value unit note input high voltage vih (ac) 0.8 x vddq v 1 input low voltage vil (ac) 0.2 x vddq v 1 input differential voltage, ck and ck# inputs vid (ac) 1.4 v 1 input differential cross point voltage, ck and ck# inputs vix (ac) vddq/2 with vdd=vddq v input signal slew rate slew 1 v/ns 1 output load cl 15 pf note : 1. vdd = vddq. figur e 6.1 wave form and timing reference figure 6.2 output load
AS4C32M16MD1 confidential 74 rev. 2 .0/february 2014 7. package outline information 7.1 60 - ball fbga package (8.0 x 9.0) < top view > symbol dimension (mm) min. typ. max. a - - 1.025 a1 0.250 0.300 0.350 b 0.400 0.450 0.5 00 d 7.900 8.000 8.100 e 8.900 9.000 9.100 d1 6.400 bsc. e1 7.200 bsc. ed 0.800 bsc. ee 0.800 bsc. aaa 0.15 bbb - - 0.200 ccc - - 0.120 ddd - - 0.080 n 60 ff 0.90 hh 0.80 < bottom view >
AS4C32M16MD1 confidential 75 rev. 2 .0/february 2014 alliance memory inc. reserves the rights to change the specifications and products without notice. alliance memory, inc., 551 taylor way, su ite #1, san carlos, ca 94070, usa tel: +1 650 610 6800 fax: +1 650 620 9211

▲Up To Search▲

Price & Availability of AS4C32M16MD1

	To Download AS4C32M16MD1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .